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Omni
General Description
ision
TM
Advanced Information Preliminary Datasheet OV7930 Color CMOS Analog CAMERACHIPTM Applications
* * * * * * * * * Video Conferencing Video Phones Video E-mail PC Multimedia Toys Security Surveillance Finger Printing Medical and Dental Equipment
The OV7930 (color) is a high performance quarter-inch CMOS CAMERACHIPTM designed for all applications requiring a small footprint, low voltage, low power consumption and low cost color video camera. The device supports NTSC composite video output and can directly interface with a VCR TV monitor or other 75 ohm terminated input with 2X standard TV signal range. The OV7930 CAMERACHIPs require only a single 5-volt DC power supply and have been designed for very low power operation.
Features
* * * * * * * Single chip 1/4" lens video camera Composite video: NTSC Sensitivity boost (+27 dB)/AGC ON/OFF Automatic exposure/gain/white balance External frame sync capability Aperture correction SCCB programmable controls: - - - - - - - * * * * Color saturation Brightness Hue White balance Exposure Gain Gamma curve
Key Specifications
Array Size Power Supply Without Loading Power With 75 ohm Requirements Loading Image Area Auto Electronic Exposure Time Minimum Illumination (3000K) S/N Ratio Dynamic Range Pixel Size Dark Current Fixed Pattern Noise Package Dimensions 510 x 492 5 VDC + 5% 20 mA < 35 mA 4.00 mm x 3.08 mm 1/60s - 6.3s < 2.0 Lux > 46 dB > 70 dB 7.86 m x 6.25 m < 100 mV/s < 0.03% VPEAK-TO-PEAK 0.45 in. x 0.45 in.
Figure 1 OV7930 Pin Diagram
AWB1S SIO_D 27 AVDD BKLT SIO_C 26 AGND 1 ABRT 3
- Aperture correction Gamma correction (0.45) ON/OFF Low power consumption +5 volt only power supply Wide dynamic range, anti-blooming, zero smearing
4
2
28
NC VREQ VRCHG NC
5 6 7 8 9 10 11
25 24 23
FASTB PWDN FODD/HGAIN VHS/MIR GAMMA FSI DGND
Ordering Information
Product OV7930 (Color, VGA, NTSC, CVO) Packages
OV7930
22 21 20 19
NC
CLCC-28, PLCC-28
CVO OVDD
12 EVDD
13 EGND
14 SCCB_E
15 VPXO/VFLP
16 XCLK1
17 XCLK2
18 DVDD
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OV7930
Color CMOS Analog CAMERACHIPTM
Omni
ision
Functional Description
This section describes the various functions of the OV7930. Refer to Figure 2 for the functional block diagram of the OV7930.
Figure 2 Functional Block Diagram
AMP Column Sample/Hold
Channel Control
Analog Signal Processor (ASP)
NTSC Video Encoder
CVO
Row Select
Image Array (528 X 500)
Gain Control
Balance Control
ASP Control
Clock/Timing Generator and Control Logic
Control Register Bank
SCCB Slave Interface
AWB1S
VHS
FASTB
PWDN
GAMMA
XCLK1
XCLK2
RESET
FODD
FSI
VPXO
BKLT
ABRT
Video Standards
NTSC TV standards are implemented and available as output in the OV7930 CAMERACHIP. Note that the accuracy and stability of the crystal clock frequency is important to avoid unwanted color shift in the TV video system. A 14.31818 MHz crystal is recommended when using the OV7930 CAMERACHIP.
Image Sensor Functions White Balance
The function of white balance in the OV7930 CAMERACHIP is to adjust and calibrate the image device sensitivity on the primary (RGB) colors to match the color cast of the light source. The Auto White Balance (AWB) can be enabled or disabled by SCCB register bit COMD[1] (see "COMD" on page 12).
Video Format
The OV7930 CAMERACHIP supports Composite (CVBS) video format only. Composite signals are generated from the built-in NTSC TV encoder.
Mirror and Vertical Flip
The OV7930 has pin control functions: * Mirror (pin22 - see "VHS/MIR" on page 4) * VFLIP (pin 15 input - see "VPXO/VFLP" on page 4)
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SCCB_E
SIO_C
SIO_D
Omni
ision
Functional Description
These two functions can be controlled separately using SCCB register bit COME[6] (see "COME" on page 12) for the mirror function and register bit COMJ[0] (see "COMJ" on page 13) for the vertical flip function.
Additional Picture Controls
The OV7930 CAMERACHIP provides additional picture control functions to enhance image quality and chip performance.
Multi-Chip Synchronize
The OV7930 CAMERACHIP provides the multi-chip Synchronize function where one chip works as the master and all others as slave devices. The master chip provides the frame synchronize signal through the FODD pin (pin 23 - see "FODD/HGAIN" on page 5). All slave devices accept the frame synchronize signal through the FSI pin (pin 20 - see "FSI" on page 4). This mode allows all devices to synchronize together.
Automatic Gain Control (AGC)
The default gain range is 1x - 8x while the user can set the gain range up to 4x or 16x.
Brightness Control
Brightness can be controlled either by internal automatic algorithms or by the user through the following SCCB register bits: * BRT[7:0] (see "BRT" on page 11)
Chip Configuration
The OV7930 CAMERACHIP has been designed for ease-of-use in many stand-alone applications. Most of the on-chip functions are configurable by connecting the appropriate pins high (logic "1") or low (logic "0") through a 10 K resistor. The CAMERACHIP reads the input pins at power up which enable user-defined default configurations. The OV7930 CAMERACHIP also has a SCCB slave interface for programmable access to all registers functions. Refer to OmniVision Technologies Serial Camera Control Bus (SCCB) Specification for detailed usage of the serial control port. NOTE Once the SCCB interface is enabled (pin 14 see "SCCB_E" on page 4), the following pin assignment functions will be ignored and functions will be defined by the related SCCB register. These pins are: * ABRT (pin 3) * BKLT (pin 4) * VFLIP (pin 15) * GAMMA (pin 21) * MIR (pin 22) * HGAIN (pin 23) * FASTB (pin 25)
Gamma Correction
The OV7930 has luminance and chrominance Gamma correction through the GAMMA pin (pin 21 - see "GAMMA" on page 4).
Backlight Control
The OV7930 manages backlight conditions through register bit COME[4] (see "COME" on page 12).
Color Saturation
Color saturation can be updated manually through the SCCB register bits SAT[7:4] (see "SAT" on page 11).
Hue Adjustment
Image hue can be adjusted through the SCCB register bits HUE[5:0] (see "HUE" on page 11).
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OV7930
Color CMOS Analog CAMERACHIPTM
Omni
ision
Pin Description
Table 1
Pin Number 01 02 03
Pin Description
Name AGND AVDD ABRT Pin Type Power Power Input Default (V) 0 5 0 Analog ground Analog Power (+5 VDC) Auto brightness control ON/OFF Backlight selection Function/Description
04
BKLT
Input
0
0: 1:
OFF ON
05 06 07 08 09 10 11 12 13 14
NC VREQ VRCHG NC NC CVO OVDD EVDD EGND SCCB_E
-- Analog Analog -- -- Output Power Power Power Input
-- 2.5 3.6 -- -- -- 5 5 0 5
No connection Internal reference Internal reference No connection No connection Composite video output, 2X standard NTSC TV signal Analog power for video output (+5 VDC) Analog power (+5 VDC) Analog ground SCCB interface enable signal, active low Valid pixels detect output. CLK is asserted on this pin during the active image period. Power up initial pin value will be latched as vertical flip ON/OFF control. 0: 1: OFF ON
15
VPXO/VFLP
I/O
0
16 17 18 19 20
XCLK1 XCLK2 DVDD DGND FSI
Input Output Power Power Input
-- -- 5 0 0
Crystal clock input. 14.31818 MHz for NTSC Crystal clock output Digital power (+5 VDC) Digital ground Frame synchronizing signal input Gamma function ON/OFF
21
GAMMA
Input
5
0: 1:
OFF ON
22
VHS/MIR
I/O
0
Vertical/Horizontal SYNC output. Power up initial pin value will be latched as mirror function ON/OFF control. 0: 1: OFF ON
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ision
Pin Description
Table 1
Pin Number
Pin Description
Name Pin Type Default (V) Function/Description Even/odd field flag and frame synchronize signal output. Power up initial pin value will be latched as AGC gain range control. 0: 1: AGC gain 1x - 4x AGC gain 1x - 8x
23
FODD/HGAIN
I/O
0
Power down mode selection 24 PWDN Input 0 0: 1: OFF ON
AEC/AGC mode selection 25 FASTB Input 0 0: 1: 26 27 28 SIO_C SIO_D AWB1S Input I/O Input -- -- 0 Fast mode Normal mode
SCCB serial interface clock SCCB serial interface data I/O After power up, first high pulse edge will trigger one shot AWB. System performs fast AWB only when this pin is high at this mode.
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OV7930
Color CMOS Analog CAMERACHIPTM
Omni
ision
Electrical Characteristics
Table 2 Operating Conditions
Parameter Operating temperature Storage temperature Operating humidity Storage humidity Min 0 -40 TBD TBD Max 40 125 TBD TBD Unit C C
Table 3
Symbol Supply VDD IDD
DC Electrical Characteristics (0C < TA < 85C)
Parameter Min Typ Max Unit
Supply voltage (AVDD, DVDD, OVDD, EVDD) Supply current in VDDs (without loading)
4.75 --
5 20
5.25 --
V mA
Digital Inputs VIL VIH CIN Input voltage LOW Input voltage HIGH Input capacitor 3.5 10 1.0 V V pF
Digital Outputs VOH VOL Output voltage HIGH Output voltage LOW 4 0.6 V V
SCCB (SIO_C and SIO_D) VIL VIH SIO_C and SIO_D SIO_C and SIO_D -0.5 3.5 0 5 1 VDD + 0.5 V V
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ision
Electrical Characteristics
Table 4
Symbol
AC Characteristics (TA = 25C, VDD = 5V)
Parameter Min Typ Max Unit
Clock Input/Crystal Oscillator fOSC Resonator frequency Load capacitor Parallel resistance Rise/fall time for external clock input Duty cycle for external clock input CVO Analog Video Output Parameters VTO_P VTO_B VSYNC Ro I/O Pin Isource Isink Output pin source current (Output = 1.5v) Output pin sink current (Output = 3v) 8 8 10 10 12 12 mA mA Video peak signal level Video black signal level Video sync pulse amplitude Video output load -- -- -- -- 2.0 0.58 0.58 75 -- -- -- -- V V V -- 40 -- 14.31818 33 1 5 50 -- 60 -- MHz pF M ns %
Miscellaneous Timing tSYNC tPU tPD tPZ External FSI cycle time Chip power up time Power up delay time Power up low-z delay -- -- -- -- 2 -- 10 1000 -- 100 -- -- field s s s
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OV7930
Color CMOS Analog CAMERACHIPTM
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ision
Timing Specifications
The OV7930 timing is standard NTSC TV timing. Figure 3 shows the NTSC timing and signal range. The OV7930 outputs 2X standard TV signals.
Figure 3 NTSC Timing and Signal Range
T h =63.49us
V TO_P = 200 IRE
Thblk = 10.08 s
Thsync = 4.76 s
v set = 8 IRE vsync = 83 IRE
3.58 MHz Color Burst 9 cycle 80 IRE p_p
(A) HORIZONTAL TIMING FOR NTSC
VHSYNC
FIELD 1
523
524
525
1
2 EQUALIZING
3
4
5
6
7
8 EQUALIZING
9
10
11
12
VERTICAL SYNC
FIELD 2
261
262
263
264
265
266
267
268
269
270
271
272
273
274
EQUALIZING
EQUALIZING
(B) VERTICAL TIMING FOR NTSC
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ision
Timing Specifications
Figure 4 SCCB Timing Diagram
tF t LOW SIO_C t SU:STA SIO_D IN tAA t DH t HD:STA t HD:DAT t SU:DAT tSU:STO t HIGH tR
t BUF
SIO_D OUT
SCCB_E
Table 5
Symbol fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH
SCCB Timing Specifications
Parameter Clock Frequency Clock Low Period Clock High Period SIO_C low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time SCCB Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 Min Typ Max 400 Unit KHz s ns ns s ns ns s ns ns ns ns
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OV7930
Color CMOS Analog CAMERACHIPTM
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ision
OV7930 Light Response
Figure 5 OV7930 Light Response
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Register Set
Register Set
Table 6 provides a list and description of the Device Control registers contained in the OV7930. The device slave addresses are 80 for write and 81 for read.
Table 6
Address (Hex) 00 01 02
Device Control Register List
Register Name GAIN BLUE RED Default (Hex) 00 80 80 R/W RW RW RW AGC Gain Control Blue Channel Gain Control MSB, 8 bits (LSB 2 bits in register BRLOW[1:0] (see "BRLOW" on page 11). Red Channel Gain Control MSB, 8 bits (LSB 2 bits in register BRLOW[5:4] (see "BRLOW" on page 11). Saturation Control Bit[7:4]: Saturation adjustment 0000: Lowest 1111: Highest Bit[3:0]: Reserved Hue Adjustment Control Bit[7:6]: Reserved Bit[5]: Hue control ON/OFF 0: OFF 1: ON Bit[4:0]: Hue control setting * Range: -20 to +20 (10000 in the middle) Reserved Brightness Adjustment Control * Range: [00] to [FF] Description
03
SAT
80
RW
04
HUE
10
RW
05
RSVD
XX
-
06
BRT
80
RW
Note: If auto brightness is enabled, this register will be automatically updated by internal control. If auto brightness is disabled, the user can update brightness value. Sharpness Adjustment Bit[7:4]: Sharpness ON/OFF threshold Bit[3:0]: Sharpness adjustment Reserved Blue/Red Channel Gain LSBs Bit[7:6]: Reserved Bit[5:4]: Red channel AWB gain two lower bits Bit[3:2]: Reserved Bit[1:0]: Blue channel AWB gain two lower bits Reserved Common Control B Bit[7]: Edge enhancement ON/OFF 0: OFF 1: Bit[6:0]: ON Reserved 11
07 08-09
SHP RSVD
D4 XX
RW -
0A
BRLOW
00
RW
0B-0D
RSVD
XX
-
0E
COMB
96
RW
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OV7930
Table 6
Address (Hex) 0F 10 11 12 13
Color CMOS Analog CAMERACHIPTM Device Control Register List
Register Name RSVD VER MIDH MIDL AEC Default (Hex) XX 01 7F A2 82 R/W - R R R RW Reserved Version number Manufacturer ID Byte -- High Manufacturer ID Byte - Low Exposure Control Value * Range: [00] to [82] Tex = (2 x AEC[7:0] + 1) x 63.5 s (Read only = 0x7F) (Read only = 0xA2) Description
Omni
ision
14
COMD
1F
RW
Common Control D Bit[7:6]: AEC/AGC algorithm analyze image area selection 00: Whole image 01: Lower two-thirds image 10: Lower one-half image 11: Lower one-third image Bit[5:3]: Reserved Bit[2]: AGC ON/OFF 0: OFF 1: ON Bit[1]: AWB ON/OFF 0: OFF 1: ON Bit[0]: AEC ON/OFF 0: OFF 1: ON Common Control E Bit[7]: SRST 1: Initiates soft reset. All registers are set to default values after which the chip resumes normal operation. Bit[6]: Mirror image selection 0: Normal 1: Output mirror image Vertical sync option (see "COMG" on page 13 for details) Backlight exposure mode ON/OFF 0: OFF 1: ON Reserved AGC gain ceiling selection - combined with COMJ[3] (see "COMJ" on page 13) as follows: 0: 1x to 4x 1: 1x to 8x/16x Reserved
15
COME
04
RW
Bit[5]: Bit[4]:
Bit[3]: Bit[2]:
Bit[1:0]:
16
COMF
44
RW
Common Control F Bit[7:3]: Reserved Bit[2]: Banding filter ON/OFF 0: OFF 1: ON Bit[1:0]: Reserved Version 1.1, January 15, 2003
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ision
Register Set
Table 6
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W Description Common Control G Bit[7]: Fast AGC/AEC algorithm ON/OFF 0: OFF 1: ON Bit[6:5]: Reserved Bit[4]: FODD pin (pin 23 - see "FODD/HGAIN" on page 5) output signal selection - combined with COME[5] (see "COME" on page 12) as follows: COMG[4] 0 0 1 Bit[3:0]: Reserved COME[5] 0 1 X FODD (pin 23) VSYNC every field VSYNC every two fields FODD (odd field flagged)
17
COMG
95
RW
18
AECPT
A5
RW
AEC/AGC Luminance Level Control Bit[7:4]: Low level luminance percentage Bit[3:0]: High level luminance percentage Note: Stable condition is AECPT[7:4] + AECPT[3:0] > 0x0E. AEC/AGC Luminance Level Control in Backlight Mode Bit[7:4]: Low level luminance percentage in backlight mode Bit[3:0]: High level luminance percentage in backlight mode Note: Stable condition is BKPT[7:4] + BKPTT[3:0] > 0x0E.
19
BKPT
59
RW
1A-1C
RSVD
XX
-
Reserved Common Control J Bit[7]: Pixel clock polarity selection 0: Normal 1: Revised pixel clock output Bit[6:4]: Reserved Bit[3]: AGC gain ceiling - in effect only if COME[2] = "1" (see "COME" on page 12) 0: 8X 1: 16X Bit[2]: Reserved Bit[1]: NTSC with 50 Hz light compensation. In effect only when COMD[0] = "1" (see "COMD" on page 12) and COMF[2] = "1" (see "COMF" on page 12) Bit[0]: Vertical flip selection 0: Normal 1: Vertical flip output image Reserved AEC/AGC Fast mode threshold Bit[7:4]: Fast AEC/AGC low level percentage threshold Bit[3:0]: Fast AEC/AGC high level percentage threshold Reserved
1D
COMJ
30
RW
1E-20 21 22-33
RSVD VPT RSVD
XX A4 XX
- RW -
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings. Version 1.1, January 15, 2003 Proprietary to OmniVision Technologies 13
OV7930
Color CMOS Analog CAMERACHIPTM
Omni
ision
Package Specifications
The OV7930 uses either a 28-pin ceramic package or 28-pin plastic package. Refer to Figure 6 for ceramic package information, Figure 7 for plastic package information, and Figure 8 for the array center on the chip.
Figure 6 OV7930 Ceramic Package Specifications
.450 SQ .008 .350 SQ .006 .011 MIN .013 MIN B/F EXPOSURE 5 8 .014 TYP .010 x 45 o CHAMFER PIN 1 INDEX .300 SQ .005 .020 TYP 1 28 28 28 1 7 6 4 .083 .01 .060 .006 .020 .002 .020 .002 .020 .002 5 .012 R TYP . .022 .004 .001 to .005 TYP 4 .050 .004 .300 .005 .075 .010 11 .050 TYP 12
11 12
9
.409 .004 1
PIN NO. 1 INDEX
20 20 19 .007 MAX B/F PULL BACK .110 REF TYP .200 .005 .040 TYP 21 22 25
.025 .003 23 26 .012 R TYP . 26 .008 R REF TYP 25 .035 MIN. .085 TYP MP-2 MP-3 .040 REF (METALLIZED) CERAMIC KYOCERA A440 (BLACK) MP-4 19 .009 R REF TYP .015 MIN TYP 18
Table 7
OV7930 Ceramic Package Dimensions
Dimensions Millimeters (mm) 11.43 + 0.20 SQ 2.11 + 0.25 0.51 + 0.05 7.62 + 0.13 SQ 1.02 + 0.1 0.64 x 2.16 0.64 x 1.27 1.27 + 0.10 1.91 + 0.25 7.62 + 0.13 10.41 + 0.10 SQ 0.55 + 0.05 Inches (in.) .450 + .008 SQ .083 + .01 .020 + .002 .300 + .005 SQ .040 + .004 .025 x .085 .025 x .050 .050 + .004 .075 + .010 .300 + .005 .409 + .004 SQ .022 + .002 Version 1.1, January 15, 2003
Package Size Package Height Substrate Height Cavity Size Castellation Height Pin #1 Pad Size Pad Size Pad Pitch Package Edge to First Lead Center End-to-End Pad Center-Center Glass Size Glass Height 14 Proprietary to OmniVision Technologies
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ision
Package Specifications
Figure 7 OV7930 Plastic Package Specifications
.093 .004 .042 .002 .300 .004 .050 .004 .050 TYP 4 5 .012 x 45 o 11 12 .022 .002 .001 to .005 TYP 12 9 .075 .004 .028 .002 11 8 7 6 .450 SQ .004 .350 SQ .006 .275 SQ .004 5 4
Pin 1 Index 1
.406 .004
.010 x 45 o Chamfer Pin 1 Index
1 28
1
28
28
20 26 25 19 18 18 21 19 .035 MIN. .085 TYP .025 .003 TYP .009 R REF TYP 22 25
23 26
.028 .002 (Metallized)
Table 8
OV7930 Plastic Package Dimensions
Dimensions Millimeters (mm) 11.43 + 0.10 SQ 2.35 + 0.1 0.70 + 0.05 7.00 + 0.10 SQ 1.07 + 0.05 0.64 x 2.16 0.64 x 1.27 1.27 + 0.10 1.90 + 0.10 7.62 + 0.10 10.30 + 0.10 SQ 0.55 + 0.05 Inches (in.) .450 + .004 SQ .093 + .004 .028 + .002 .275 + .004 SQ .042 + .002 .025 x .085 .025 x .050 .050 + .004 .075 + .004 .300 + .004 .406 + .004 SQ .022 + .002
Package Size Package Height Substrate Height Cavity Size Castellation Height Pin #1 Pad Size Pad Size Pad Pitch Package Edge to First Lead Center End-to-End Pad Center-Center Glass Size Glass Height
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OV7930
Color CMOS Analog CAMERACHIPTM
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ision
Sensor Array Center
Figure 8 OV7930 Sensor Array Center
1
Scan Origin Die Sensor Array
Package Center (0,0) Positional Tolerance s Die shift (x,y) = 0.15 mm (6 mils) max. Die tilt = 1 degrees max. Die rotation = 3 degrees max.
Array Center (276m, -89m)
NOTES: 1. This drawing is not to scale and is for reference only. 2. As most optical assemblies invert and mirror the image, the chip is typically mounted with pin one oriented down on the PCB.
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ision
Package Specifications
Note:
* All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision', `CameraChip' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. Sunnyvale, CA USA (408) 733-3030
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OV7930
Color CMOS Analog CAMERACHIPTM
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ision
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